Can anyone tell me the general criteria for about the boundary conditions for device with gate enabled? I am using the Boundary condition as shown in the attached file corresponding to my device geometry. Is it correct ?
Can you please tell me the effect of dirichlet boundary conditions at the top of the gate (top(B)) and dirichlet at the bottom(bottom(B))?
Hey Ash.
I digged out a calculation I did some time ago of a similar system, that might spread some light on this matter. Starting with the bottom gate:
since your gate is pretty much covering the entire bottom face (making it effectively dirichlet), you will only see little effect of what you choose here. If you set it to dirichlet, then every point in the bottom that is not covered by your gate will be forced to zero. This will make the effect of the gate very localized in space in the A,B plane, but all in all this does not really matter in this simulation.
The choice for the top plane matters a lot. If you set it to dirichlet, you force the electrostatic potential to be zero at the top and by doing so, you will force the electric field strength to be gate voltage over length of cell in that direction. The electric field strength would be very strong, in other word the gate potentials has too drop off much faster. If you set it to Neumann, the field strength can vary and the potential drop off can be as long as required,
so if the desired is to model vacuum at the top, i would personally go with Neumann there.
